A Hardware-Software Partitioning and Scheduling Algorithm for Dynamically Reconfigurable Embedded Systems
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چکیده
Dynamically reconfigurable embedded systems (DRESs) target an architecture consisting of generalpurpose processors and field programmable gate arrays (FPGAs), in which FPGAs can be reconfigured in run-time to achieve cost saving. In this paper, we describe a hardware-software partitioning and scheduling approach for DRESs. Previous work only took configuration time into account, without considering partial reconfiguration. With partial reconfiguration, the scheduling on FPGAs becomes a constrained placement problem, whereas scheduling on application-specific integrated circuits (ASICs) is a serialization problem. Here we present a method, based on genetic algorithm (GA) and an improved list scheduling algorithm, which can tackle multirate, real-time, periodic systems. The different variants of algorithm are evaluated by a randomly generated testbench. Keywords— Dynamic reconfiguration, FPGA, co-design, Partitioning, Scheduling
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تاریخ انتشار 2000